In a variety of data processing contexts a number of different interrupt signals I.sub.1, I.sub.2, . . . are generated at various times during operation, the generation of each interrupt signal signifying an occurrence of the event corresponding to the interrupt signal. Thus, if and when, say, the i'the event occurs, then the i'th interrupt signal I.sub.i is generated. Each event can in general occur at random (asynchronously), and when each such event occurs it signifies that certain computer-type action should be taken corresponding to the event, i.e., signifies that a corresponding computer-type instruction should be executed, as by a synchronous microprocessor. Typically, the microprocessor is integrated in a signle semiconductor circuit chip, and the interrupt signals are generated in other circuit chips.
In such data processing systems, more than a single event can occur essentially simultaneously, and hence more than a single interrupt signal can be generated at once. Moreover, on occasion the events occur so rapidly one after the other that the corresponding interrupt signals are generated so rapidly that, if the interrupt signals are delivered directly to the target machine, then the target synchronous machine cannot execute the corresponding instructions fast enough to keep up with the events. Therefore, it becomes necessary to have an interrupt controller arrangement, i.e, means for temporarily storing, as by queuing, the different incoming interrupt signals before delivering them to the target synchronous machine (typically a microprocessor).
In prior art, an interrupt controller arrangement, for thus temporarily storing the interrupt signals I.sub.1, I.sub.2, I.sub.3, . . . , typically involves the use of an array of latches L.sub.1, L.sub.2, L.sub.3, . . . . The arrival of interrupt signal I.sub.i sets the corresponding latch L.sub.i to logic "high", i.e., to binary digital "1", for recording and storing the information as to the arrival of the interrupt signal. Each such latch is reset to "0" immediately after readout of the latch. Each of the latches thus temporarily stores a single bit B.sub.1, B.sub.2, B.sub.3, . . . corresponding to whether or not the corresponding interrupt signal I.sub.1, I.sub.2, I.sub.3, . . . has been generated since the previous time the latch had been accessed for readout. Thus, for example, when the i'th event occurs, the i'th interrupt signal I.sub.i is generated and arrives at the i'th latch L.sub.i, whereby the i' th latch is set--i.e., the state of the i'th bit B.sub.i becomes a binary digital "1"; and when the i'th latch L.sub.i is accessed for readout, it is reset to "0"--i.e., the i'th bit B.sub.i becomes "0". The array of latches is scanned periodically, e.g., once during every time period T, so that each of the latches is accessed for readout, one after another in sequence, and is immediately thereafter reset to "0", once and only once during every such period. This period T, the scanning period, typically is selected to be sufficiently short so that no event occurs twice during any period. Alternatively, the second occurrence of an event during a given period is not considered meaningful, because it is not effective in changing the state of the corresponding latch (and hence it ultimately is not effective in commanding the target synchronous machine to execute the corresponding instructions a corresponding second time). Accordingly, it will be assumed that the period T is selected to be short enough that no event occurs twice within any such period, or that the second occurrence of the event is considered as not meaningful. As a further alternative, a second latch can be supplied for an event that can occur twice within any period T. In any case, when a given latch L.sub.i is accessed for readout, the latch L.sub.i enables or does not enable--depending upon whether it is then set (to "1") or reset (to "0")--a memory stack to be written with an encoded interrupt word (string of bits) W.sub.i corresponding to the latch L.sub.i and hence corresponding to the i'th event. Thus different encoded words W.sub.i are written or not written in the memory stack depending upon whether the bit B.sub.i is then a "1" or a "0". Typically the memory stack is a FIFO (first in, first out) memory stack. In any case, after each latch is thus accessed for readout it is reset to "0", the stored bit B.sub.i therein is "0", and the latch L.sub. i retains this "0" until the corresponding interrupt signal I.sub.i once again is generated and arrives at this latch. Finally, the memory stack stores in a queue each of the encoded interrupt words W.sub.i thus written into it and delivers each of these words W.sub.i in sequence--typically first in, first out--to the target synchronous machine, one word for each synchronous timing cycle of the machine. Note that each machine cycle and each scanning period T in general are independent of each other, i.e., have no correlation.
A serious problem that arises in using such an interrupt controller arrangement is the requirement of a separate latch for each interrupt signal, i.e., a separate latch for recording and temporarily storing the occurrences of each event. Thus if there are n different events, typically as many as 50 or more, there are n different interrupt signals I.sub.i, and hence there must be n different latches L.sub.i and n separate access time intervals constituting each scanning period T. Thus, for an access time t, the period T must be as long as at least nt in duration. It would therefore be desirable to have an arrangement in which the required number of latches are significantly reduced, whereby the scanning period T can be correspondingly reduced.